1. Field of the Invention
The present invention relates to a method for fabricating a MOS type semiconductor memory device, and more specifically to a method for selectively forming a low impurity concentration source/drain region and a high impurity concentration source/drain region in the process of fabricating a MOS type semiconductor memory device including a memory cell zone and a peripheral circuit zone formed in the same substrate. Here, the term "source/drain region" used in this specification should be understood to means a region which acts as a source region or a drain region, or both.
2. Description of Related Art
In conventional MOS type semiconductor memory devices, both of a memory formed of a number of memory cells and a peripheral circuit include MOS transistors having source and drain regions formed by an ion implantation of a high dosage. However, the ion implantation of the high dosage for the formation of source/drain regions has resulted in damage of the device, which deteriorates a junction leakage characteristics, and also has made it difficult to form a shallow junction. These disadvantages will inevitably decrease a reliability of an electric charge hold characteristics of memory cells, with increase of the fineness and the integration density of memory cells, which is a tendency of advancement of technology.